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NIT Delhi Recruitment 2017 Various Posts (05 Vacancies)

National Institute of Technology (NIT) Delhi invites applications from Indian Nationals for direct recruitment of Secretary and Accountant. The closing date for receipt of applications is 17th February 2017.



No of posts

Age Limit

Pay Band with Grade Pay



Not exceeding 30 years

PB-2 (₹ 9300-34800) with Grade Pay of ₹ 4200/-



Not exceeding 30 years

PB-2 (₹ 9300-34800) with Grade Pay of ₹ 4200/-

Educational Qualifications:

Secretary ->

(1) Matric with 12th Standard pass or equivalent from a recognized Board or University. Minimum speed of 100 w.p.m in Stenography.
(2) Desirable - The candidate having higher qualification, knowledge of Computers and working experience with Govt. Institutions like IITs/ NITs/ Govt./ Autonomous bodies shall be given preference.

Accountant ->

(1) First Class Bachelor's Degree in Commerce with Honors in Accountancy/Finance or equivalent grade from a recognized University or Institute (In Universities without a system of Honors degree, equivalent number of courses) (OR) Master's Degree in Commerce/MBA (Finance) from a recognized University or Institute with excellent academic record.
(2) Knowledge of computer application viz. word processing, spread sheet and computer based accounting software.
(3) Desirable - (i) A Chartered or Cost Accountant degree holder will be given preference. (ii) The employees working in IITs/ NITs/ Centre Govt./ Autonomous Bodies, the deserving candidates will be given preference and suitable moderation if any, may be granted by the screening committee appointed by the competent authority.

Selection Process: Written Test, Skill/ Proficiency Test and Interview

Application Fee: The Application fee is to be enclosed alongwith the Application Form in the form of Demand Draft of ₹ 500/- for General/ OBC candidates and ₹ 250/- for SC/ST/PWD candidates in favor of "Director, NIT Delhi".

How to Apply: Application complete in all respects including Self-Attested Photocopies and Documents mentioned in the list, should reach in the Institute on or before 17/02/2017 up to 05:00 PM.

Detailed Notification >>

National Institute of Technology (NIT) Delhi Walk-in-Interview for various positions (purely on contract basis) of the various positions are invited under Special Manpower Development Programme (SMDP) - Chip-to-System Design (C2SD) funded by Department of Electronics and IT, (DeitY) Govt. of India, in the department of Electronics and Communication Engineering. The Walk in interview will be held on 8th February 2017.

About: NIT Delhi - An autonomous Institute under the aegis of Ministry of HRD, Government of India.


No of Vacancy

Essential Qualification

Project Associate


B. Tech in Electronics and Communication Engineering (ECE) with minimum CGPA of 6.5 and having working experience in VLSI related software.

Lab Engineer


B.E. / B. Tech. in Electronics or Electronics & Communication or Computer Science or Electrical Engineering, with a minimum CGPA of 6.5 or minimum 60 % marks, having a working knowledge on Windows, Linux and VLSI Software tools.

Interested candidates are requested come for an Walk-in-interview according to following schedule:

Date -> 08/02/2017
Time -> 2:00 PM onwards
Venue -> Committee Room, NIT Delhi A-7, Institutional Area, Nareal 110040, Delhi. INDIA.

Applicants must report at least one hour before the commencement of interview time with required documents. A cover letter addressed to The Chief Investigator, SMDP C2SD Programme, National Institute of Technology Delhi.

Detailed Notification >>

NIT Delhi invites applications from highly motivated and eligible candidates for the post of Junior Research Fellowship (JRF) in SERB-DST funded sponsored research project. The last date for receipt of applications is 12th February 2017.

Name of the Post

No of Vacancy


Duration of Appointment

Junior Research Fellowship (JRF)


INR 25,000/- per month will be paid throughout the duration of project

Initially the appointment will be made for one year with can be extended upto 3 (three) years purely based on the performance. The position is co-terminus with the project

Project Title: "Higher-Order DC-DC Converters for Power Management of DC Nano-Grid in Futuristic Smart Buildings"
Funding Agency: Science and Engineering Research Board (SERB) - DST, Government of India
Name of the Project Investigator (PI): Dr. Anmol Ratna Saxena
Department: Electrical and Electronics Engineering
Duration of the project: 3 Years (2016-2019)

Essential Qualification:

(1) M. Tech. or M.E. degree in Electrical Engineering / Electrical and Electronics Engineering with specialization in Power Electronics and Drives with first division.
(2) B. Tech. or B.E. degree in Electrical Engineering / Electrical and Electronics Engineering with first division.

Selection Process: Shortlisted candidates will be called for Interview.

How to Apply: Candidate possessing the requisite qualification and experience should apply, in the attached format along with their updated CV latest by midnight of 12/02/2017. The Duly signed Scan copy of Application Form along with the scan copies of mark sheets/documents must be sent to Dr. Anmol Ratna Saxena (PI), only through email, at following address: with CC to Please write "Application JRF in the Department of EEE" in the subject line.

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